A conventional CMOS output buffer circuit having an output V.sub.OUT for delivering output signals of high and low potential levels in response to data signals at the input V.sub.IN is illustrated in FIG. 1. An output pullup driver transistor P1 sources current to the output V.sub.OUT from a high potential rail V.sub.CC. An output pulldown driver transistor N1 sinks current from the output V.sub.OUT to a low potential rail GND. A pullup predriver circuit in the form of inverter stage P2, N2 is coupled to a gate node of the output pullup driver transistor P1 for controlling the conducting state of P1 in response to data signals at the input V.sub.IN. A pulldown predriver circuit in the form of inverter stage P3, N3 is coupled to a gate node of the output pulldown driver transistor N1 for controlling the conducting state of transistor N1 in response to data signals at the input V.sub.IN.
The CMOS output buffer circuit of FIG. 1 is a tristate output circuit with a tristate enable signal input OE. The tristate enable signal input OE is coupled directly to pulldown predriver tristate transistors P5, N5 and through inverter I4 to pullup predriver tristate transistors P4, N4. With the OE signal low (OE signal high) the tristate output enable circuit does not interfere in the normal operation of the pullup and pulldown predriver circuits. The output pullup and pulldown driver transistors and output V.sub.OUT therefore operate in the normal bistate mode. With OE signal high (OE signal low) the output pullup and pulldown driver transistors P1, N1 are disabled and present a high impedance at the output V.sub.OUT.
The rise and fall times for output signal transitions between high and low potential levels at the output V.sub.OUT are functions of the size of the respective output pullup and pulldown driver transistors P1, N1, the speed of switching or driving of the output driver transistors P1, N1 by the respective pullup and pulldown predriver circuits, and the size of the load capacitance being charged or discharged at the output V.sub.OUT. Typically the edge rates or slew rates of output signals and the rise and fall times at the edges of the output signals are determined primarily by the sizes of the output pullup and pulldown transistors P1, N1 and the sizes of the pullup and pulldown predriver circuit transistors P2, N2, P3, N3. More recently, advanced CMOS output buffer circuits are characterized by high drive, high speed output signals with very fast edge rates. A variety of circuit techniques are used to control the transition time or edge rate of such output signals.
For example in the Jeffrey B. Davis U.S. Pat. No. 4,961,010, transition times and edge rates of output signals are controlled by bifurcated turn on of the output pullup and pulldown transistors for reducing switching induced noise. In the Davis U.S. patent application Ser. No. 483,927, filed Feb. 22, 1990, for OUTPUT BUFFER CIRCUIT WITH SIGNAL FEED FORWARD FOR REDUCING SWITCHING INDUCED NOISE, the transition time is prolonged and edge rate reduced by an initial early turn on of the output pullup and pulldown transistors using feed forward signals. In the Davis U.S. Pat. No. 5,036,222, the transition time at edges of the output signals is prolonged or not in response to the voltage sensed at the output. In the Alan c. Rogers U.S. Pat. No. 5,049,763 issued Sep. 17, 1991 for ANTI-NOISE CIRCUITS, turn on of the output driver transistors may be suppressed by an anti-noise transistor functioning as an active variable resistance coupled in the control gate path of the respective output driver transistor. The conductivity of the anti-noise transistor varies inversely with sensed power rail noise effectively controlling fall or rise times in response to the ground bounce or V.sub.CC droop in the power rails.
Feedback capacitors have also been used in linear buffer circuits to control slew rate. Such linear buffer circuits, however, are operational amplifiers with very slow edge rates in the order of micro-seconds (.mu.S) and using feedback capacitance in the order of micro-farads (.mu.F). To applicant's knowledge, feedback capacitors have not been used to control edge rate in high speed switching digital circuits and using feedback capacitance many orders of magnitude smaller in the picofarad (pF) range. Nor have digitally addressable and selectable edge rate control circuits been incorporated in such digital circuits.